The present invention relates generally to integrated circuits, and more particularly to a system and method for controlling an SRAM sense amplifier clock.
Semiconductor memory devices are used in a wide variety of contexts. One type of memory is a static random access memory (SRAM). This type of memory is considered static since it will retain its state without need for refresh. A system that utilizes an SRAM will typically have dedicated SRAM memory chips or will include other the memory on-chip with other circuitry, e.g., embedded memory. The present invention is applicable in either case.
FIG. 1 shows a simplified schematic diagram of an array 10 of SRAM cells 12. One cell 12 is shown in detail and includes a cross-coupled pair of inverters 14 and 16. In the typical embodiment, each inverter includes an n-channel metal oxide semiconductor (NMOS) transistor coupled in series with a p-channel metal oxide semiconductor (PMOS) transistor. The input of one of the inverters is coupled to the output of the other inverter so that state will be latched.
To select one of the memory cells 12, the row decoder 18 drives one of the wordlines 20 to a high voltage level. The high voltage on the wordline will cause the pass transistors 22 and 24 to become conductive thereby transferring the state of the memory cell to the respective pair of bitlines 26 and 28. As shown in the figure, the bitline pair will include a bitline BL (labeled 26) and a complementary bitline BLb (labeled 28) that carries a level that is opposite that on the bitline.
Sense amplifier 30 amplifies the voltage difference between the complementary bitlines 26 and 28. The data can then be routed out of the array by circuitry that is not shown. The sense amplifier 30 is enabled by an enable or clock signal labeled SA_EN. The timing of this sense amplifier signal SA_EN is important. If the sense amplifier 30 is triggered before the bitline pair 26/28 has been sufficiently charged then the output of the sense amplifier 30 could be incorrect. On the other, any unnecessary delay in the sense amplifier enable signal SA_EN will lower the operation speed of the memory array.
The preferred embodiment of the present invention provides a technique for controlling the timing of the sense amplifier enable signal. This preferred technique compensates for leakage of unselected devices that might slow down the selected devices ability to charge up the bitline. In one aspect, the concept is to use an additional dummy off-cell bitline to monitor and simulate the leakage effect. When leakage occurs on real bit line circuit, the sense amplifier will automatically slow down his enable timing.
In known memory circuits, there are at least two methods in controlling a sense amplifier clock: the delay chain method and the dummy bit line current tracking method. This patent is aimed to overcome leakage problems with these, as well as other methods.
In a first embodiment, an additional dummy bit line can be provided to control the supply voltage of the delay chain in a traditional delay chain sense amplifier clock control. When bit line leakage occurs in the core array, the dummy bit line, which includes cells like those in the array, will drop its voltage as well. This drop will cause the delay chain speed to slow down.
In a second embodiment, a low active circuit can be used to select from multiple delay chain. This selection can be based on the additional dummy bit line voltage level. The slower delay chain will be turn on while the more bit line leakage.
In a third embodiment, the dummy bitline can be used to directly control the loading of the delay chain. When more leakage occurs on the dummy cells, the loading of delay chain will increase. This increased loading will cause the speed of the delay chain to slow down.
In the case that utilizes the dummy bit line current tracking method, the circuit can use a dummy on-cell bitline and a dummy off-cell bit line along with a voltage level (or current level) subtractor to simulate the real bit line pair. The difference voltage between the dummy on bitline and the dummy off bitline will control the sense amplifier clock timing.
The above concept can also be used to accomplish fine control method. In this embodiment, a dummy on-cell bitline and a dummy off-cell bit line can be used with a voltage level subtractor to control the supply voltage of single delay chain or to select one of multiple delay chain. Another method is to use a dummy on-cell bitline and a dummy off-cell bitline to control the loading of a delay chain. The more on-cell current the more the loading is decreased and the more off-cell leakage, the more loading increased.
In certain embodiments, the present invention provides an effective method to overcome the leakage influence in voltage differences between the two bitlines in a complementary pair. If leakage occurs, the sense amplifier will automatically slow down its timing. During normal condition when no leakage occurs, the sense amplifier will not be affected. As a result, one advantage is that the preferred embodiment keeps the same speed as traditional designs in normal condition, and only slows down the sense amplifier speed to match the bitline speed when leakage occurs.